Moore's Law states that the number of semiconductor devices, (e.g., transistors), per unit area will double every 18–24 months. While other factors such as design improvements contribute to the rapid growth, one of the fundamental drivers of this inexorable density increase is the ever-shrinking minimum feature size of semiconductors. For example, a common minimum feature size of modern semiconductors is 0.15 microns.
A modern integrated circuit, IC, for example a flash memory device, may have millions to hundreds of millions of devices made up of complex, multi-layered structures that are fabricated through hundreds of processing steps. Those structures, for example a gate stack, are formed by repeated deposition and patterning of thin films on a silicon substrate, also known as a wafer.
For example, a structure above the surface of a wafer may be formed by depositing polysilicon over the entire wafer, followed by the application of a photosensitive polymer layer, known as photoresist. The photoresist-covered wafer is exposed to a light source, usually a narrow band of ultraviolet light, for example, from a mercury lamp. A mask is used to shield portions of the wafer from the light, creating an exposure pattern on the wafer. The light energy changes the chemical nature of the photoresist. A developing solution is then used to remove the photoresist in the areas exposed to the light source. This sequence of steps is known as photolithography.
The pattern of remaining photoresist (which was the mask pattern) is then recreated in the underlying film (e.g., the layer of polysilicon) by etching away the material that is not protected by photoresist. In a subsequent processing step, the photoresist is chemically removed.
Prior Art FIGS. 1A through 1D illustrate a conventional photolithography process used to form a gate stack of a floating gate memory cell 10. In Prior Art FIG. 1A, oxide layer 112 has been formed by conventional means over wafer 110. A layer of photoresist 120 is then deposited above the oxide layer.
In Prior Art FIG. 1B, light energy 140 is directed at photoresist layer 120. A mask structure 130 blocks some areas of photoresist layer 120 from receiving light energy 140.
In Prior Art FIG. 1C, the photoresist has been developed. Areas of photoresist that received (were exposed to) the light energy 140 are removed by the developing process. During the exposure process, reflected light causes standing waves 169a to form on the edges of the photoresist resulting in uneven side-walls of the photoresist. Wafer 110 subsequently undergoes an etching process. As described previously, an etching process removes material where photoresist material is not present.
As depicted in Prior Art FIG. 1D, after etching, and a subsequent removal of the remaining photoresist material, substantial portions of memory cell 10 are formed. As a result of standing waves 169a in the photoresist, the resulting memory gate cell 10 has a contoured sidewall 169b. Contoured or non-linear sidewalls of a photoresist decrease the accuracy of the subsequent etching processes thus reducing the accuracy of the final dimensions of the channel length. As stated above, Moore's Law predicts the number of components per a unit area to double every 18–24 months. To maintain steady reduction in feature size of modern semiconductors, manufacturing processing must be more accurate than ever. The formation of standing waves in photoresist prevents semiconductor manufacturing to achieve adequate accuracy when producing channel lengths smaller than 0.015 microns.
The gate length, generally corresponding approximately with minimum feature size 18, is one of the most critical features of a Metal Oxide Semiconductor, MOS, device. When a field-effect transistor in a MOS device is in the “on” state, it conducts current between a drain and a source. The shorter the distance between a drain and a source, the shorter the distance that charge carriers, e.g., electrons or “holes,” must travel. In general, charge carriers travel at a constant speed in a uniform material. (Speed may vary according to differing types of material and different types of charge carriers.) Therefore, a short channel produces a faster or higher speed transistor. Up to a certain point, which generally varies from design to design, shorter channels corresponding to faster transistors, are considered desirable. However, if a channel becomes too short, the device may suffer from what is known as the “short channel effect.”
As channel length grows shorter, threshold voltage, the voltage required to turn on a transistor, begins to decrease and leakage current increases. These effects are commonly referred to in the semiconductor arts as the “short channel effect.” An increase in leakage current is particularly onerous in flash memory devices as flash has found wide acceptance in very low power applications, for example mobile phones, due to the ability of flash to retain information without applied power. Increases in leakage current may have a significant deleterious effect on total power consumption of the flash device and the product using the flash device.
A problem with the photolithography process results from the highly reflective nature of the materials and surfaces of semiconductor devices. Prior Art FIG. 2A illustrates a deleterious effect of reflective surfaces upon photolithography. As a result of reflections from surface 110, standing waves caused the photoresist 120 to cure unevenly thus forming contoured sidewalls.
Unfortunately, standing wave 169a produces widely varying levels of light energy intensity within photoresist layer 120. In general, the light energy intensity within photoresist layer 120 will vary from zero to twice the level of the incident radiation. In regions of photoresist layer 120 receiving zero light energy, the desirable chemical changes in the polymer(s) comprising photoresist layer 120 do not occur. In regions of photoresist layer 120 receiving more light energy than is incident, damage may occur. In other regions, varying levels of chemical changes may occur corresponding to the varying levels of light energy received. As an unfortunate consequence, the photoresist material is not changed uniformly. After developing, portions of photoresist may remain in regions intended to be removed, resulting in incorrectly formed semiconductor structures as illustrated in Prior Art FIG. 2B. For example, a gate length 18 may be unintentionally increased because of incomplete etching resulting from such standing waves.
Prior Art FIG. 3 illustrates one well-known solution to the problem of standing waves. Layer 220 is applied over reflective surface 210 prior to the application of photoresist layer 120. Through careful control of the optical properties and thickness of layer 220, reflections from reflective surface 210 can be eliminated prior to having a deleterious effect within photoresist layer 120. Layer 220, applied at the bottom of photoresist layer 120 is known as a Bottom Anti-Reflective Coating, or BARC. A conventional BARC is typically a silicon oxynitride, SiNxOy, and is deposited by chemical vapor deposition (CVD).
Unfortunately, the thickness of a bottom anti-reflective coating is critical to its function. For example, to perfectly cancel reflected light with incident light (along the normal to the surfaces), a BARC should have an effective optical thickness of one quarter of a wavelength (λ/4). The wavelength of light used to expose the photoresist will typically determine the minimum feature size of the semiconductor device as determined by the Rayleigh criteria. Consequently, ever-smaller wavelengths of light energy are being employed forever-smaller minimum feature dimensions. As the wavelengths decrease, the λ/4 thickness of the BARC decreases and the allowable variation of BARC thickness to achieve a desirable percentage decrease in reflected energy also decreases. As an unfortunate consequence, it is becoming commercially infeasible to apply BARCs with the required thickness tolerances.
Reflectivity at an interface (normal incidence) is given by the relation:
                    R        =                                                                                                              n                    ~                                    1                                -                                                      n                    ~                                    2                                                                                                  n                    ~                                    1                                +                                                      n                    ~                                    2                                                                          2                                    (                  relation          ⁢                                          ⁢          1                )            Where n is the refractive index (real) of a material and k is the coefficient of extinction (complex) of a material. By definition, ñ1=n1+ik1 is the complex index of refraction for material 1, where n is the refractive index (real) of a material and k is the coefficient of extinction (complex) of a material. In this example, material 1 (ñ1) has a non-zero complex portion. Consequently, if material 2 has a purely real index of refraction, then the modulus of ñ1−ñ2 can never be identically zero, and the reflectivity can not be zero. Consequently, an anti-reflective coating, typically with a complex index of refraction, can not completely cancel reflections from a reflective material with a real index of refraction, for example a dielectric or damascene metal.
If an ARC was made thick enough, standing waves in the photoresist could be substantially reduced. Consequently, a very thick ARC creates more problematic issues than the standing waves in the photoresist such as hills and valleys. In addition, a thick ARC is very difficult to remove and can cause contamination of the semiconductor device.
Semiconductor processing equipment is extremely expensive. Fundamental semiconductor processing steps, e.g., implantation, diffusion and etching, typically require long periods of development and extensive qualification testing. Implementing a new fabrication process requires considerable resources on the part of the semiconductor manufacturer. A manufacturer may have to alter or entirely revamp process libraries and process flows in order to implement a new fabrication process. Additionally, re-tooling a fabrication line is very expensive, both in terms of direct expenses as well as in terms of opportunity cost due to the time required to perform the re-tooling. Consequently, any solution to standing waves within photoresist should be compatible with existing semiconductor processes and equipment without the need for revamping well established tools and techniques.